1. Field of the Invention
The present invention relates to semiconductor ICs, particularly those having sub-micron rules, e.g., 1 .mu.um or less, and method of making the same.
2. Description of the Prior Art
The semiconductor ICs are becoming more and more highly integrated in recent years, and sizes of the unitary semiconductor devices are about to become sub-micron. In order to form such very minute pattern, the conventional way of using ultraviolet ray exposure method comes to the limit of technology, and therefore in these years, far-UV rays, X-rays, electron beams, ion beams, etc. are being used. However, apparatus to carry out the abovementioned far-UV, X-ray, electron beams, or ion beams exposurings are very much expensive, and more over the exposuring of intensity of X-rays, electron beams or ion beams are low and accordingly takes a long exposuring time, and therefore it is not suitable for a mass production of the semiconductor ICs.
As semiconductor IC having repeated structure, there is a CCd as shown in FIG. 1, which is fragmental perspective view of an essential part of the IC which has three kinds of electrodes. The CCD is substantially an IC utilizing MOS capacitors, and its structure has, for instance, an ion implanted region P.sup.+ for channel stopping formed from a surface of P-type silicon substrate 1, and thereon three kinds of electrodes P1, P2 and P3 are formed with oxide film thereunder on the surface of the substrate 1. When a positive potential is applied to the electrode P1, P-type majority carriers in the silicon substrate 1 is expelled, and thereby potential wells 2 are formed, and the ion-implanted channel stopper region P.sup.+ limits expansion of the potential wells 2. The potential wells 2 store therein thermally excited minority carriers. When potentials are impressed in turn on the electrodes P1, P2 and P3, then the potential wells 2 move in the silicon substrate 1 along the parts under the electrodes P.sub.1, P.sub.2 and P.sub.3, and therefore the minority carriers are transferred with the transferring of the potential well. In the example of FIG. 1, pitch L from one electrode P.sub.1 to the next same kind electrode P.sub.1 is width of a unit cell, and the pitch L is as large as six times of an electrode width l in the ordinary design.
In general, a CCD comprises 96 or 256 or more number of the above-mentioned unit cells in a line and its function is limited, for instance, in application for delay device or imaging apparatus. In such application case, function to be carried out by three kinds of electrodes P.sub.1, P.sub.2 and P.sub.3 is to carry minority carriers, and there is no other function in comparison with transistors in IC. As other CCDs than that shown in FIG. 1, there are proposed those of two phase type or C4D structure which is regarded as having minimum size. In the CCD of C4D structure, effective barrier width as long as half the minimum designed electrode width has been realized by ion implantation method, and a length of four times the minimum line width is one unit cell length.
As is described above, in the CCD applying MOS capacitors, there is a relation EQU L=2kT (k=1, 2, 3, . . .) (1)
between the minimum designed electrode length T and the unit cell length L. But the function of this device is limited only for transferring minority carriers which are immediately under the electrodes, and its application is narrow. On the other hand, in BBDs which serve similar function with that of CCD, such structures of applications of transistors are proposed as a junction type FET wherein a MOSFET switch is formed in n-type epitaxial sillicon layer or a Schottky barrier FET. But in these structure, one unit cell length to form the transistor can not be limited to the minimum size. Accordingly, there is no particular size relation between the one unit cell length and the minimum size as proposed in the CCD.
In the case of semiconductor IC memory which is a representative example of IC having repeated pattern, neither gate positions, nor electrode positions, nor contact-window positions is not selected to be 2kT for the minimum line width T. Furthermore, in one unit cell, for instance, of MOS memory, enhancement type transistors and depletion type transistors are employed in combination. In such configuration, the gate lengths and gate widths and also polycrystalline silicon wiring width are different from each other and not unified. Accordingly when designing the plan view pattern of such IC, the practice is that the individual transistors are designed one by one and the designing is not efficient.
In large type transistors such as power transistors, which have large mutual conductance Gm, a zigzag pattern is formed as shown in FIG. 2, wherein crosswise sectional configuration has pattern of repetitions of gate electrodes. In such transistors, its Gm has the following relation EQU Gm.varies.aW/L.sub.c ( 2)
where, L.sub.c is channel length, W is gate width and a is vertical height in a direction normal to PN junction. In order to increase Gm, it is necessary to decrease the channel length L.sub.c and increase the gate width W. Therefore such configuration as shown in FIG. 2(a) wherein source S and drain D are disposed in parallel rows and in zigzag disposition with a zigzag shape gate inbetween, is necessary.
In FIG. 2(b) which shows the cross section along the sectional plane II-II', gate electrodes 7 is formed by polycrystalline silicon on a gate oxide film 6, by utilizing known photolithographic etching And source region S and drain region D are formed on both sides of the gate by defusing an impurity in the substrate 5, and thereon source electrode 8 and drain electrode 8' are provided.
In the above-mentioned zigzag-structure large power transistor, when the gate electrode is formed in zigzag pattern in order to obtain a larger gate width and shorter channel length, undesirable strong electric fields are centered at turning points of the zigzag-shaped gate, and undesirable trouble is likely to be induced when the IC is highly integrated, and accordingly the zigzag pattern is not practical
In semiconductor IC memory as a representative example of repetition pattern, gate positions or electrode positions or contact window positions have not been selected to be repetition interval of 2kT for minimum line width T. Also in one device of MOS type IC, where enhancement type FET and depletion type FET are used in combination, their gate lengths, gate widths and wiring widths are not unified, thereby simplification of design of plan view configuration is not achievable.
Conventional exposuring methods to make semiconductor IC are as follows. Hitherto, ultraviolet ray exposure in photolithographic method has been widely used, but its resolution limit is about 1 .mu.m limited by defraction and interference of light, and it has not been possible to obtain submicron line width. FIG. 3 schematically shows a configuration where contact exposuring on a semiconductor substrate is carried out. A mask pattern 12 provided on a glass plate is put on a wafer 13 coated with a photoresist film 14. Then, UV-rays 16 are projected on the wafer through the glass plate 11 and then parts of the photoresist film 14 which is not covered by the mask pattern 12 is exposed to the UV-rays, so that unexposed parts 15 disposed identical to the mask pattern 12 is obtained. In this method, due to effect of light defraction from edges of the mask pattern 12, practical resolution is limited to about 1 .mu.m. Alternatively, there is compressed projection method where the mask pattern is projected in smaller size on the photoresist film, but even with the method, practical limit of resolution is about 0.8 .mu.m.
FIG. 4 schematically shows principle of conventional holography. Way of recording a hologram on a wafer W is described. Coherent rays from a light source such as laser source is divided by a beam splitter BS into transmission rays 17 and reflected rays 18, and the transmission rays 17 are projected on an object B, and rays reflected from the object B are projected on the wafer W. On the other hand, the reflected rays 18 are after reflection by mirror M lead onto the wafer W as reference rays. Then the rays reflected from the object B and the reference rays from the mirror M mutually interfere, and as a result of the interference, amplitude modulation of light is produced on a photosensitive film on a wafer to form a hologram. For reproducing a holography image from the hologram, the same reference rays 18 are projected onto the hologram on the wafer W, and then by observing from a point E an image is observed as if the object B exists at the position where it has been, as a result of defracted rays from the hologram. In this case, the pattern to be recorded on the hologram is an interference stripe pattern produced as a result of interference between rays reflected from the object and the reference rays, and information of a point on the object effect all the area of the hologram and the hologram as such has no clear pattern noticeable to human eyes, which produces the holography image only when the reproducing rays are emanated. Though there is a method to produce a hologram by digital signal, the hologram as such of this case is only dot pattern of dark and bright dots, and the holography image is produced only when reference rays are projected on the hologram.
FIG. 5 schematically shows a device to produce a holographic fringe by interference of two light beams. In this apparatus, an incident parallel light beam 19 is divided by a beam splitter BS into transmission rays 21 and reflection rays 20 both are reflected by mirror M and M' respectively and the reflected transmission rays 21 and reflected rays 20 are projected both on a wafer W and superposed thereon. Thus a conjugate two light beams are incident on the wafer W, and accordingly interference fringe is recorded on a photoresist film on the wafer W. In this method, an arbitrarily desired pattern can not be formed, but only black and white stripe corresponding to interference fringe as shown in FIG. 6 is obtainable.
As has been described, the conventional methods only can produce about 0.8 .mu.m line width pattern by photolithographic method or only simple parallel pattern upto about 0.1 .mu.m line width as a result of interference fringe of coherent two light beams or vague hologram pattern which has such vague and rough pattern as not usable for semiconductor device pattern.